| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Supply Voltage (DC) | 2.00 V to 6.00 V |
| Case/Package | TSSOP |
| Number of Outputs | 8 Output |
| Output Current | 7.80 mA, 7.80 A |
| Number of Circuits | 8 Circuit |
| Number of Bits | 8 Bit |
| Propagation Delay Max (tpd) | 32.0 ns |
| Polarity | Non-Inverting |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Output Current Drive | -1.00 mA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Cut Tape (CT) |
The SN74HC373PWR is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An OE\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
● High-current 3-state true outputs can drive up to 15 LSTTL loads
● Full parallel access for loading
● Eight high-current latches
● 80µA Maximum low power consumption
● Typical tpd = 13ns
● ±6mA Output drive at 5V
● 1µA Maximum low input current
● Green product and no Sb/Br
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