| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 29.0 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 2.00 V to 6.00 V |
| Case/Package | DIP |
| Output Current | 5.20 mA |
| Number of Circuits | 2 Circuit |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 37.0 ns |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Output Current Drive | -1.00 mA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
The SN74HC109N is a dual positive-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. It can perform as toggle flip-flop by grounding K\ and tying J high. It can perform as D-type flip-flops if J and K\ are tied together.
● High-current outputs drive up to 10 LSTTL loads
● 40µA Maximum low power consumption
● 12ns Typical tpd
● ±4mA Output drive at 5V
● 1µA Maximum low input current
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Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40℃ to 85℃
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