● High-Performance Digital Media Processor
● 720-MHz, 900-MHz C64x+™ Clock Rates
● 1.39 ns (-720), 1.11 ns (-900) Instruction Cycle Time
● 5760, 7200 MIPS
● Eight 32-Bit C64x+ Instructions/Cycle
● Fully Software-Compatible With C64x/Debug
● Commercial Temperature Ranges (-720, -900 only)
● Industrial Temperature Ranges (-720, -900 only)
● VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
● Eight Highly Independent Functional Units With VelociTI.2 Extensions:
● Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
● Two Multipliers Support Four 16 x 16-bit Multiplies (32-bit Results) per Clock Cycle or Eight 8 x 8-bit Multiplies (16-Bit Results) per Clock Cycle
● Load-Store Architecture With Non-Aligned Support
● 64 32-bit General-Purpose Registers
● Instruction Packing Reduces Code Size
● All Instructions Conditional
● Additional C64x+™ Enhancements
● Protected Mode Operation
● Exceptions Support for Error Detection and Program Redirection
● Hardware Support for Modulo Loop Auto-Focus Module Operation
● C64x+ Instruction Set Features
● Byte-Addressable (8-/16-/32-/64-bit Data)
● 8-bit Overflow Protection
● Bit-Field Extract, Set, Clear
● Normalization, Saturation, Bit-Counting
● VelociTI.2 Increased Orthogonality
● C64x+ Extensions
● Compact 16-bit Instructions
● Additional Instructions to Support Complex Multiplies
● C64x+ L1/L2 Memory Architecture
● 256K-bit (32K-byte) L1P Program RAM/Cache [Direct Mapped]
● 256K-bit (32K-byte) L1D Data RAM/Cache [2-Way Set-Associative]
● 1408KB L2 Unified Mapped RAM/Cache [Flexible Allocation]
● Supports Little Endian Mode Only
● External Memory Interfaces (EMIFs)
● 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O)
● Asynchronous 16-Bit Wide EMIF (EMIFA)
● Up to 128M-Byte Total Address Reach
● 64M-Byte Address Reach per CE Space
● Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM)
● Synchronous Memories (SBSRAM and ZBT SRAM)
● Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
● Enhanced Direct-Memory-Access (EDMA) Controller (64 IndependentChannels)
● 3-Port Gigabit Ethernet Switch Subsystem
● Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
● One UART (With RTS and CTS Flow Control)
● One 4-wire Serial Port Interface (SPI) With Two Chip-Selects
● Master/Slave Inter-Integrated Circuit (I2C Bus™)
● Two Telecom Serial Interface Ports (TSIP0/1)
● Multichannel Audio Serial Port (McASP)
● Ten Serializers and SPDIF (DIT) Mode
● 16/32-Bit Host-Port Interface (HPI)
● Advanced Event Triggering (AET) Compatible
● 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/SlaveInterface Conforms to PCI Specification 2.3
● VLYNQ™ Interface (FPGA Interface)
● On-Chip ROM Bootloader
● Individual Power-Saving Modes
● Flexible PLL Clock Generators
● IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
● 32 General-Purpose I/O (GPIO) Pins (Multiplexed With Other DeviceFunctions)
● Package:
● 529-pin nFBGA (ZUT suffix)
● 19x19 mm 0.8 mm pitch BGA
● 0.09-µm/6-Level Cu Metal Process (CMOS)
● 3.3-V and 1.8-V I/O, 1.2-V Internal (-720,-900)
