description
●The TMS320C6202 and TMS320C6202B devices are part of the TMS320C62xfixed-point DSP generation
●in the TMS320C6000DSP platform. The C62xDSP devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
●High-Performance Fixed-Point Digital Signal Processors (DSPs) −TMS320C62x
●−5-, 4-, 3.33-ns Instruction Cycle Time
●−200-, 250-, 300-MHz Clock Rate
●−Eight 32-Bit Instructions/Cycle
●−1600, 2000, 2400 MIPS
●C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package†
●C6202B and C6203B GNZ and GNY Packages are Pin-Compatible
●VelociTIAdvanced Very-Long-Instruction Word (VLIW) C62xDSP Core
●−Eight Highly Independent Functional Units:
● −Six ALUs (32-/40-Bit)
● −Two 16-Bit Multipliers (32-Bit Result)
●−Load-Store Architecture With 32 32-Bit General-Purpose Registers
●−Instruction Packing Reduces Code Size
●−All Instructions Conditional
●Instruction Set Features
●−Byte-Addressable (8-, 16-, 32-Bit Data)
●−8-Bit Overflow Protection
●−Saturation
●−Bit-Field Extract, Set, Clear
●−Bit-Counting
●−Normalization
●3M-Bit On-Chip SRAM
●−2M-Bit Internal Program/Cache (64K 32-Bit Instructions)
●−1M-Bit Dual-Access Internal Data (128K Bytes)
●−Organized as Two 64K-Byte Blocks for Improved Concurrency
●32-Bit External Memory Interface (EMIF)
●−Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
●−Glueless Interface to Asynchronous Memories: SRAM and EPROM
●−52M-Byte Addressable External Memory Space
