● High-Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6201
● 5-ns Instruction Cycle Time
● 200-MHz Clock Rate
● Eight 32-Bit Instructions/Cycle
● 1600 MIPS
● VelociTI™ Advanced Very Long Instruction Word (VLIW) TMS320C62x™ DSP CPU Core
● Eight Independent Functional Units:
● Six ALUs (32-/40-Bit)
● Two 16-Bit Multipliers (32-Bit Results)
● Load-Store Architecture With 32 32-Bit General-Purpose Registers
● Instruction Packing Reduces Code Size
● All Instructions Conditional
● Instruction Set Features
● Byte-Addressable (8-, 16-, 32-Bit Data)
● 32-Bit Address Range
● 8-Bit Overflow Protection
● Saturation
● Bit-Field Extract, Set, Clear
● Bit-Counting
● Normalization
● 1M-Bit On-Chip SRAM
● 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
● 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency
● 32-Bit External Memory Interface (EMIF)
● Glueless Interface to Asynchronous Memories: SRAM and EPROM
● Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
● Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
● 16-Bit Host-Port Interface (HPI)
● Access to Entire Memory Map
● Two Multichannel Buffered Serial Ports (McBSPs)
● Direct Interface to T1/E1, MVIP, SCSA Framers
● ST-Bus-Switching Compatible
● Up to 256 Channels Each
● AC97-Compatible
● Serial Peripheral Interface (SPI) Compatible (Motorola™)
● Two 32-Bit General-Purpose Timers
● Flexible Phase-Locked Loop (PLL) Clock Generator
● IEEE-1149.1 (JTAG) Boundary-Scan Compatible
● 352-Pin BGA Package (GJC Suffix)
● 352-Pin BGA Package (GJL Suffix)
● CMOS Technology
● 0.18-µm/5-Level Metal Process
● 3.3-V I/Os, 1.8-V Internal
