The TMS320C5517AZCHA20 is a Digital Signal Processor designed for low active and standby power consumption. The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
● One or two instructions executed per cycle
● Two arithmetic and logic units (ALUs)
● Three internal data or operand read buses and two write buses
● Software-compatible with C55x Devices
● Tightly coupled FFT hardware accelerator
● One universal host-port interface (UHPI) with 16-bit muxed address or data bus
● Master and slave multichannel serial ports interface (McSPI) with three chip selects
● Master and slave multichannel buffered serial ports interface (McBSP)
● Universal asynchronous receiver/transmitter (UART)
● Direct memory access (DMA) controller serial port interface (SPI) with four chip selects
● Master and slave inter-integrated circuit (I²C Bus)
● Three inter-IC sound (I²S bus) modules for data transport
● Four core isolated power supply domains - Analogue, RTC, CPU and peripherals and USB
● Green product and no Sb/Br
