SN74LVC573APW Datasheet PDF - TI

The SN74LVC573APW is an octal transparent D Latch with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. It is specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The highimpedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches.

● Support mixed-mode signal operation on all ports

● Ioff Supports live insertion, partial power down mode and back drive protection

● Latch-up performance exceeds 250mA per JESD 17

● Green product and no Sb/Br