SN74LVC373APWR Datasheet PDF - TI

The SN74LVC373APWR is an octal transparent D Latch with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

● Supports mixed-mode signal operation on all ports

● Ioff Supports live-insertion, partial-power-down mode, and back-drive protection

● Latch-up performance exceeds 250mA per JESD 17

● Green product and no Sb/Br