| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 2.00 V to 5.50 V |
| Case/Package | TSSOP |
| Output Current | 12.0 mA |
| Number of Circuits | 4 Circuit |
| Number of Bits | 4 Bit |
| Propagation Delay Max (tpd) | 23.0 ns |
| Voltage Nodes | 5.00 V, 3.30 V, 2.50 V |
| Number of Gates | 4 Gate |
| Output Current Drive | -1.00 mA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Cut Tape (CT), Tape & Reel (TR) |
The SN74LV132APWR is a quadruple positive-NAND Gate with Schmitt-trigger inputs. The device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. Each circuit functions as a NAND gate, but because of the Schmitt-trigger, it has different input threshold levels for positive- and negative-going signals. The circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
● <0.8V at VCC = 3.3V Typical VOLP (Output ground bounce)
● >2.3V at VCC = 3.3V Typical VOHV (output VOH undershoot)
● Ioff supports live insertion, partial power down mode and back drive protection
● ESD protection exceeds JESD 22
● Latch-up performance exceeds 250mA per JESD 17
TI
NAND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin SSOP T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin TSSOP Tube
TI
NAND Gate 4Element 2IN CMOS 14Pin SOIC Tube
TI
NAND Gate 4Element 2IN CMOS 14Pin SOIC T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin SOP T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin TVSOP T/R
TI
NAND Gate 4Element 2IN CMOS 14Pin SOIC T/R
Part Datasheet PDF Search
72,405,303 Parts Datasheet PDF, Update more than 5,000 PDF files ervery day.
