| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 30.0 MHz |
| Number of Pins | 14 Pin |
| Digital Logic Level | TTL |
| Supply Voltage (DC) | 4.75 V to 5.25 V |
| Case/Package | DIP |
| Output Current | 8.00 mA |
| Supply Current | 100 µA |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 20.0 ns |
| Voltage Nodes | 5.00 V |
| Output Current Drive | -50.0 µA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube, Rail |
The SN74LS107AN is a two independent Negative-Edge-Triggered Flip-flop with J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
● 7V Input voltage
● 2V High-level input voltage
● 0.8V Low-level input voltage
TI
TEXAS INSTRUMENTS SN74LS107AN Flip-Flop, with Clear, Complementary, Positive Edge, 74LS107, JK, 15ns, 30MHz, 8mA, DIP
TI
IC: digital; JK flip-flop; Channels:2; 74LS; SMD; SO14
TI
Flip Flop JK-Type Neg-Edge 2Element 14Pin SOP T/R
TI
Flip Flop JK-Type Neg-Edge 2Element 14Pin SOIC Tube
TI
Flip Flop JK-Type Neg-Edge 2Element 14Pin SOP
TI
IC JK TYPE NEG TRG DUAL 14SO
TI
Flip Flop JK-Type Neg-Edge 2Element 14Pin SOIC T/R
TI
IC FLIP FLOP DUAL J-K 14-DIP
TI
IC FLIP FLOP DUAL J-K 14-SOIC
TI
Flip Flop JK-Type Neg-Edge 2Element 14Pin SOIC T/R
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