| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 2.00 V to 6.00 V |
| Case/Package | SOIC, PDIP |
| Number of Outputs | 4 Output |
| Contacts Type | DP4T |
| Number of Circuits | 2 Circuit |
| Number of Bits | 4 Bit |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Bandwidth | 28.0 MHz |
| Output Current Drive | -1.00 mA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
The SN74HC139N is a 2-to-4 dual Decoder/Demultiplexer designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable (G\\) input can be used as a data line in demultiplexing applications. It features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
● Targeted specifically for high-speed memory decoders and data-transmission systems
● Incorporate two enable inputs to simplify cascading and/or data reception
● Outputs can drive up to 10 LSTTL loads
● 10ns Typical tpd
● 80µA Maximum low power consumption
● ±4mA Output drive at 5V
● 1µA Maximum low input current
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