SN7497N Datasheet PDF - TI

The SN7497N is a 6-bit synchronous Binary-rate Multiplier utilizes series 54/74 TTL circuitry to achieve 32MHz typical maximum operating frequencies. These six-bit serial binary counters feature buffered clock, clear and enable inputs to control the operation of the counter and a strobe input to enable or inhibit the rate input/decoding AND-OR-INVERT gates. The outputs have additional gating for cascading and transferring unity-count rates. The counter is enabled when the clear, strobe and enable inputs are low. With the counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 64 i.e. The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used as a control for the Y output.

● Perform fixed-rate or variable-rate frequency division