| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 3.00 V (min) |
| Case/Package | SOIC |
| Data Rate | 400 Mbps |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
The SN65LVDS33PW is a quad LVDS Data Line Receiver offers the widest common-mode input voltage range in the industry. This receiver provides an input voltage range specification compatible with a 5V PECL signal as well as an overall increased ground-noise tolerance. Precise control of the differential input voltage thresholds allows for inclusion of 50mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50mV over the full input common-mode voltage range. The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The non-terminated SN65LVDS series is available for multidrop or other termination circuits. The receivers can withstand ±15kV human-body model (HBM) and ±600V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage.
● Integrated 110R line termination resistors on LVDT products
● Active failsafe assures a high-level output with no input
● Input remains high-impedance on power-down
● TTL inputs are 5V tolerant
● Pin-compatible with the AM26LS32, SN65LVDS32B, µA9637and SN65LVDS9637B
● Green product and no Sb/Br
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