● 32- and 64-Bit 250-MHz Floating-Point DSPs
● Single Event Latch-Up Immune to LET = 117 MeV cm2/mg
● Radiation Tolerance: 100 kRad TID (Si)
● Upgrades to C67x+ CPU From C67x DSP Generation:
● 2X CPU Registers [64 General-Purpose]
● Compatible With the C67x CPU
● Enhanced Memory System
● 256K-Byte Unified Program and Data RAM
● 384K-Byte Unified Program and Data ROM
● Single-Cycle Data Access From CPU
● Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory
● External Memory Interface (EMIF) Supports
● 133-MHz SDRAM (16- or 32-Bit)
● Asynchronous NOR Flash, SRAM (8-,16-, or 32-Bit)
● NAND Flash (8- or 16-Bit)
● Enhanced I/O System
● High-Performance Crossbar Switch
● Dedicated McASP DMA Bus
● Deterministic I/O Performance
● dMAX (Dual Data Movement Accelerator) Supports:
● 16 Independent Channels
● Concurrent Processing of Two Transfer Requests
● 1-, 2-, and 3-Dimensional Memory-to-Memory and Memory-to-Peripheral Data Transfers
● Circular Addressing Where the Size of a Circular Buffer (FIFO) is not Limited to 2n
● Table-Based Multi-Tap Delay Read and Write Transfers From and To a Circular Buffer
● Three Multichannel Serial Ports
● Transmit and Receive Clocks up to 50 MHz
● Six Clock Zones and 16 Serial Data Pins
● Universal Host-Port Interface (UHPI)
● 32-Bit-Wide Data Bus for High Bandwidth
● Muxed and Non-Muxed Address and Data
● Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options
● Two Inter-Integrated Circuit (I2C) Ports
● Real-Time Interrupt Counter and Watchdog
● Oscillator- and Software-Controlled PLL
● Available Temperature Ranges
● M-Temp (–55°C to 125°C Tcase)
● W-Temp (–55°C to 115°C Tcase)
● 256-Pin, 0.5-mm, Ceramic Quad Flatpack (CQFP) [HFH Suffix]
● Engineering Evaluation (/EM) Samples are Available(1)
