PCA9654EDTR2G Datasheet PDF - ON Semiconductor

The PCA9654E provides 8 bits of General Purpose parallel Input/Output (GPIO) expansion for IThe PCA9654E consists of 8−bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master may set the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master.The PCA9654E open−drain interrupt (INTb) output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power−on reset sets the registers to their default values and initializes the device state machine.Three hardware pins (AD0, AD1, AD2) vary the fixed IC bus address and allow up to 64 devices to share the same I

●Features

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● VDD Operating Range: 1.65 V to 5.5 V

● SDA Sink Capability: 30 mA

● 5.5 V Tolerant I/Os

● Polarity Inversion Register

● Active LOW Interrupt Output

● Low Standby Current

● Noise Filter on SCL/SDA Inputs

● No Glitch on Power−up

● Internal Power−on Reset

● 64 Programmable Slave Addresses Using 3 Address Pins

● 8 I/O Pins which Default to 8 Inputs