OMAP3530ECUS Datasheet PDF - TI

Description

●OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

●• Streaming video

●• Video conferencing

●• High-resolution still image

●The device supports high-level operating systems (HLOSs), such as:

●• Linux®

●• Windows® CE

●• Android™

●This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

●Features

●• OMAP3530 and OMAP3525 Devices:

●   – OMAP™ 3 Architecture

●   – MPU Subsystem

●• Up to 720-MHz ARM® Cortex™-A8 Core

●• NEON™ SIMD Coprocessor

●   – High-Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem

●• Up to 520-MHz TMS320C64x+™ DSP Core

●• Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)

●• Video Hardware Accelerators

●   – PowerVR® SGX™ Graphics Accelerator (OMAP3530 Device Only)

●• Tile-Based Architecture Delivering up to 10 MPoly/sec

●• Universal Scalable Shader Engine: Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality

●• Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0

●• Fine-Grained Task Switching, Load Balancing, and Power Management

●• Programmable High-Quality Image Anti-Aliasing

●   – Fully Software-Compatible with C64x and ARM9™

●   – Commercial and Extended Temperature Grades

●• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP Core

●   – Eight Highly Independent Functional Units

●• Six ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle

●• Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle

●   – Load-Store Architecture with Nonaligned Support

●   – 64 32-Bit General-Purpose Registers

●   – Instruction Packing Reduces Code Size

●   – All Instructions Conditional

●   – Additional C64x+ Enhancements

●• Protected Mode Operation

●• Exceptions Support for Error Detection and Program Redirection

●• Hardware Support for Modulo Loop Operation

●• C64x+ L1 and L2 Memory Architecture

●   – 32KB of L1P Program RAM and Cache (Direct Mapped)

●   – 80KB of L1D Data RAM and Cache (2-Way Set-Associative)

●   – 64KB of L2 Unified Mapped RAM and Cache (4-Way Set-Associative)

●   – 32KB of L2 Shared SRAM and 16KB of L2 ROM

●• C64x+ Instruction Set Features

●   – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)

●   – 8-Bit Overflow Protection

●   – Bit Field Extract, Set, Clear

●   – Normalization, Saturation, Bit-Counting

●   – Compact 16-Bit Instructions

●   – Additional Instructions to Support Complex Multiplies

●• ARM Cortex-A8 Core

●   – ARMv7 Architecture

●• TrustZone®

●• Thumb®-2

●• MMU Enhancements

●   – In-Order, Dual-Issue, Superscalar Microprocessor Core

●   – NEON Multimedia Architecture

●   – Over 2x Performance of ARMv6 SIMD

●   – Supports Both Integer and Floating-Point SIMD

●   – Jazelle® RCT Execution Environment Architecture

●   – Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack

●   – Embedded Trace Macrocell (ETM) Support for Noninvasive Debug

●Applications

●• Portable Navigation Devices

●• Portable Media Player

●• Digital Video Camera

●• Portable Data Collection

●• Point-of-Sale Devices

●• Gaming

●• Web Tablet

●• Smart White Goods

●• Smart Home Controllers