NB6L11DG Datasheet PDF - ON Semiconductor

The NB6L11DG is an 1:2 enhanced differential Clock or Data Fan-out Buffer/Translator has the same pin-out and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the device is optimized for the systems that require LOW skew, LOW jitter and LOW power consumption. Differential input can be configured to accept single-ended signal by applying an external reference voltage to unused complementary input pin. Input accepts LVNECL, LVPECL, LVTTL, LVCMOS, CML or LVDS. The outputs are 800mV ECL signals.

● Open input default state

● Q outputs will default low with inputs open or at VEE

● LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input compatible

● 14mA Typical low power supply current

● 150ps Typical propagation delay

● 5ps Typical within device skew

● 75ps Typical rise/fall times