| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 5.50 V (max) |
| Case/Package | QFN-16 3 x 3 |
| Halogen Free Status | Halogen Free |
| Number of Bits | 1 Bit |
| Polarity | Non-Inverting, Inverting |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.
●Features
●---
● |
● Maximum Input Clock Frequency > 4 GHz Typical
● 330 ps Typical Propagation Delay
● 145 ps Typical Rise and Fall Times
● Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
● Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
ON Semiconductor
8 Pages / 0.14 MByte
ON Semiconductor
5 Pages / 0.28 MByte
ON Semiconductor
2.5V/3.3V/5V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination
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