The LMK04828BEVM evaluation kit for LMK04828 industry"s highest performance clock conditioners with JEDEC JESD204B support. The dual loop PLLatinum architecture enables sub 100fs jitter (12KHz to 20MHz) using a low noise VCXO module. The dual loop architecture consists of two high performance phase locked loops (PLL), a low noise crystal oscillator circuit and a high performance voltage controlled oscillator (VCO). The first PLL provides a low noise jitter cleaner function while the second PLL performs the clock and SYSREF generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close in phase noise (offsets below 50KHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO.
● Ultra low RMS jitter performance
● Three redundant input clocks with LOS
● Precision digital delay, fixed or dynamically adjustable
● 25ps step analog delay
● 3.15V to 3.45V operation
● 50% duty cycle output divides
● 3.15V to 3.45V operation
●This evaluation module is not a finished electrical equipment and not intended for consumer use.
