| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 3 Pin |
| Voltage Rating (DC) | -25.0 V |
| Current Rating | -120 mA |
| Case/Package | SOT-23 |
| Drain to Source Resistance (on) (Rds) | 13.0 Ω |
| Polarity | P-Channel |
| Power Dissipation | 350 mW |
| Drain to Source Voltage (Vds) | -25.0 V |
| Breakdown Voltage (Drain to Source) | -25.0 V |
| Continuous Drain Current (Ids) | 120 mA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Cut Tape (CT), Tape & Reel (TR) |
The FDV302P is a P-channel logic level enhancement-mode Digital FET produced using Fairchild"s proprietary high cell density DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. It is designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series.
● Very low level gate drive requirements allowing direct operation
● Gate-source Zener for ESD ruggedness, >6kV human body mode
● Compact industry standard surface-mount package
● Replace many PNP digital transistors (DTCx and DCDx) with one DMOS FET
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