| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 6 Pin |
| Voltage Rating (DC) | -25.0 V |
| Current Rating | -410 mA |
| Case/Package | SC-70 |
| Drain to Source Resistance (on) (Rds) | 1.10 Ω |
| Polarity | P-Channel, Dual P-Channel |
| Power Dissipation | 300 mW |
| Input Capacitance | 62.0 pF |
| Gate Charge | 1.10 nC |
| Drain to Source Voltage (Vds) | -25.0 V |
| Breakdown Voltage (Drain to Source) | -25.0 V |
| Continuous Drain Current (Ids) | -410 mA |
| Rise Time | 8.00 ns |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Cut Tape (CT) |
Dual P-Channel, Digital FET General Description These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild"s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Features Very low level gate drive requirements allowing direct operation in 3 V circuits . Compact industry standard SC70-6 surface mount package.
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