| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 6 Pin |
| Voltage Rating (DC) | 25.0 V |
| Current Rating | 220 mA |
| Case/Package | SC-70 |
| Drain to Source Resistance (on) (Rds) | 4.00 Ω |
| Polarity | N-Channel, Dual N-Channel |
| Power Dissipation | 300 mW |
| Input Capacitance | 9.50 pF |
| Gate Charge | 290 pC |
| Drain to Source Voltage (Vds) | 25.0 V |
| Breakdown Voltage (Drain to Source) | 25.0 V |
| Breakdown Voltage (Gate to Source) | 8.00 V |
| Continuous Drain Current (Ids) | 220 mA |
| Rise Time | 4.50 ns |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Cut Tape (CT) |
The FDG6301N is a dual N-channel logic level enhancement-mode Digital FET with high cell density and DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. It has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signals MOSFETs.
● Very low level gate drive requirements allowing direct operation in 3V circuits (VGS (th) <1.5V)
● Gate-source Zener for ESD ruggedness (>6kV human body model)
● Compact industry standard surface-mount-package
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