| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 147 MHz |
| Number of Pins | 84 Pin |
| Supply Voltage (DC) | 4.75 V (min) |
| Case/Package | PLCC |
| Number of Gates | 2500 Gate |
| Number of I/O Pins | 68 IO |
| TYPE | DESCRIPTION |
|---|
| Packaging | Tray |
The EPM7128SLI84-10N is an EEPROM Complex Programmable Logic Device with 2500 usable gates and 128 macro cells. MAX 3000A CPLD is a high-density, high-performance and fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5000 usable gates, ISP, pin-to-pin delays as fast as 5ns and counter speeds of up to 175.4MHz. Programmable macro cell flip-flops with individual clear, preset, clock and clock enable controls. The programmable power-saving mode for a reduction of over 50% in each macro cell.
● PCI-compliant device
● Open-drain output
● Programmable security bit for protection of proprietary designs
Altera
66 Pages / 1.45 MByte
Altera
18 Pages / 0.47 MByte
Altera
CPLD MAX 7000S Family 2.5K Gates 128 Macro Cells 100MHz CMOS Technology 5V 84Pin PLCC
Altera
CPLD MAX 7000S Family 2.5K Gates 128 Macro Cells 100MHz CMOS Technology 5V 84Pin PLCC
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