The CD74HC194E is a 4-bit CMOS bidirectional universal Shift Register with an asynchronous master RESET (MR\\). In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a low applied to the master RESET (MR\\) pin.
● Shift right, shift left, hold and reset operation modes
● Synchronous parallel or serial operation
● Asynchronous master reset
● Balanced propagation delay and transition times
● Significant power reduction compared to LSTTL logic ICs
● High noise immunity
● Direct LSTTL input logic compatibility
● CMOS Input compatibility
● 10 LSTTL Loads standard outputs
● 15 LSTTL Loads bus driver outputs
