| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 15.0 V, 18.0 V (max) |
| Case/Package | SOIC, PDIP |
| Number of Bits | 8 Bit |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Input Capacitance | 5.00 pF |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
The CD4021BE is a CMOS 8-stage parallel or serial-input/serial output Static Shift Register with common clock and parallel/serial control inputs, a single serial data input and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, "Q" outputs are also available from stages 6 and 7. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. In both types, entry is controlled by the parallel/serial control input. When parallel/serial control input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the parallel/serial control input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BE, the clock input of the internal stage is "forced" when asynchronous parallel entry is made.
● Medium speed operation
● Fully static operation
● 8 Master-slave flip-flops plus output buffering and control gating
● 100% Tested for quiescent current at 20V
● Maximum input current of 1µA at 18V
● Standardized, symmetrical output characteristics
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