CD40192BE Datasheet PDF - TI

The CD40192BE is a CMOS presettable BCD Up/Down Counter for use with multistage ripple counting and synchronous frequency dividers. This device consists of 4 synchronously clocked, gated D type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a preset/enable/control, individual clock up and clock down signals and a master reset. Four buffered Q signal outputs as well as carry/and borrow/outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the reset line. A reset is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the preset/enable/control is low. The counter counts up one count on the positive clock edge of the clock up signal provided the clock down line is high.

● Individual clock lines for counting up or counting down

● Synchronous high-speed carry and borrow propagation delays for cascading

● Asynchronous reset and preset capability

● Standardized and symmetrical output characteristics

● 100% Tested for quiescent current at 20V