The ADSP-21061KSZ-160 is a high performance commercial-grade SHARC DSP Microcomputer offers new capabilities and levels of performance. The ADSP-21061 SHARC is a 32-bit processor optimized for high performance DSP applications. It builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus. Fabricated in a high speed, low power CMOS process, the ADSP-21061 has a 20ns instruction cycle time and operates at 50 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. The ADSP-21061 SHARC represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including 1MB SRAM memory, a host processor interface, a DMA controller, serial ports and parallel bus connectivity for glue less DSP multiprocessing.
● Four independent buses for dual data fetch, instruction fetch and nonintrusive I/O
● Dual data address generators with modulo and bit-reverse addressing
● Efficient program sequencing with zero-overhead looping - single cycle loop setup
● IEEE JTAG Standard 1149.1 test access port and on-chip emulation
● 32-bit IEEE floating-point computation units-multiplier, ALU and shifter
● Dual-ported on-chip SRAM and integrated I/O peripherals a complete system-on-a-chip
● Integrated multiprocessing features
● 50MIPS, 20ns Instruction rate, single-cycle instruction execution
● 120 MFLOPS peak, 80 MFLOPS sustained performance
