GENERAL DESCRIPTION
●The ADSP-2100 Family processors are single-chip micro computers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-21xx processors are all built upon a common core. Each processor combines the core DSP architecture—computation units, data address generators, and program sequencer—with differentiating features such as on-chip program and data memory RAM, a programmable timer, one or two serial ports, and, on the ADSP-2111, a host interface port.
●FEATURES
●25 MIPS, 40 ns Maximum Instruction Rate
●Separate On-Chip Buses for Program and Data Memory
●Program Memory Stores Both Instructions and Data (Three-Bus Performance)
●Dual Data Address Generators with Modulo and Bit-Reverse Addressing
●Efficient Program Sequencing with Zero-Overhead
●Looping: Single-Cycle Loop Setup
●Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.g., EPROM )
●Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel Operation
●ADSP-2111 Host Interface Port Provides Easy Interface to 68000, 80C51, ADSP-21xx, Etc.
●Automatic Booting of ADSP-2111 Program Memory Through Host Interface Port
●Three Edge- or Level-Sensitive Interrupts
●Low Power IDLE Instruction
●PGA, PLCC, PQFP, and TQFP Packages
●MIL-STD-883B Versions Available
●SUMMARY
●16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory
●Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses
●Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter
●Single-Cycle Instruction Execution & Multifunction Instructions
●On-Chip Program Memory RAM or ROM & Data Memory RAM
●Integrated I/O Peripherals: Serial Ports, Timer, Host Interface Port (ADSP-2111 Only)
