The ADN4662BRZ is a single CMOS low voltage differential signalling (LVDS) Line Receiver offering data rates of over 400Mbps (200MHz) and ultralow power consumption. It features a flow-through pin-out for easy PCB layout and separation of input and output signals. The device accepts low voltage (310mV typical) differential input signals and converts them to a single-ended 3 V TTL/CMOS logic level. The ADN4662 and its companion driver, the ADN4661, offers a new solution to high speed, point-to-point data transmission and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).
● Flow-through pin-out simplifies PCB layout
● 2.5ns Maximum propagation delay
● High impedance outputs on power-down
● Low power design - typically 18mW
● Interoperable with existing 5V LVDS drivers
● Accepts small swing differential signal levels
● Supports open, short and terminated input failsafe
● 0V to -100mV Threshold region
