| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 73.0 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 4.50 V (min) |
| Case/Package | DIP |
| Output Current | 4.00 mA |
| Number of Bits | 1 Bit |
| Polarity | Non-Inverting, Inverting |
| Number of Gates | 2 Gate |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Not Listed by Manufacturer |
| Packaging | Tube |
The 74HCT107N is a dual negative edge triggered JK Flip-flop featuring individual J and K inputs, clock (CP\\) and reset (R\\) inputs and complementary Q and Q\ outputs. The reset is an asynchronous active low input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
● TTL Input levels
● Complies with JEDEC standard No. 7A
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