| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 96 Pin |
| Supply Voltage (DC) | 1.65 V to 3.60 V |
| Case/Package | BGA |
| Number of Outputs | 40 Output |
| Number of Bits | 16 Bit |
| Propagation Delay Max (tpd) | 3.00 ns |
| Static Current | 60.0 µA |
| Output Current Drive | -1.00 mA |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
The 74ALVCH32973ZKER is a 16-bit Bus Transceiver and Transparent D-type Latch with eight independent buffers and designed for 1.65 to 3.6V VCC operation. When the latch-enable input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE)\ input can be used to place the nine Q outputs in either a normal logic state or the high-impedance state. In the high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, LOE\ and TOE\ should be tied to VCC through pull-up resistors, the minimum values of the resistors are determined by the current-sinking capability of the drivers. The A and B I/Os and D inputs have bus-hold circuitry.
● Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors
● Latch-up performance exceeds 250mA per JESD 17
● ESD protection exceeds JESD 22
● Green product and no Sib/Br
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