74AHC573D,118 Datasheet PDF - NXP

The 74AHC573D is an octal transparent D Latch pin compatible with low-power Schottky TTL (LSTTL). It consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A LE and an OE\ are common to all latches. When pin LE is high, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is low, the latches store the information that is present at the Dn inputs, after a set-up time preceding the high-to-low transition of LE. When pin OE\ is low, the contents of the 8 latches are available at the outputs. When pin OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the OE\ input does not affect the state of the latches.

● Balanced propagation delays

● All inputs have a Schmitt trigger action

● Common 3-state output enable input

● Inputs accept voltages higher than VCC

● CMOS Input level

● Complies with JEDEC standard No. 7A