description
●The SMQ320C32 is a member of the ’320C3x generation of digital signal processors from Texas Instruments. The SMQ320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-µm triple-level-metal CMOS technology. The enhancements to the ’320C3x architecture include a variable-width external-memory interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts.
●• Military Operating Temperature Range
● − 55°C to 125°C; QML Processing
●• High-Performance Floating-Point Digital Signal Processor (DSP) SMQ320C32-50 (5 V)
● − 40-ns Instruction Cycle Time
● − 275 MOPS
● − 50 MFLOPS
● − 25 MIPS SMQ320C32-60 (5 V)
● − 33-ns Instruction Cycle Time
● − 330 MOPS
● − 60 MFLOPS
● − 30 MIPS
●• 32-Bit High-Performance CPU
●• 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
●• 32-Bit Instruction Word, 24-Bit Addresses
●• Two 256 × 32-Bit Single-Cycle, Dual-Access On-Chip RAM Blocks
●• Flexible Boot-Program Loader
●• On-Chip Memory-Mapped Peripherals:
● − One Serial Port
● − Two 32-Bit Timers
● − Two-Channel Direct Memory Access (DMA) Coprocessor With Configurable Priorities
●• Enhanced External Memory Interface That Supports 8-/16-/32-Bit-Wide External RAM for Data Access and Program Execution From 16-/32-Bit-Wide External RAM
●• SMJ320C30 and SMJ320C31 Object Code Compatible
●• Fabricated Using Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments
●• 144-Pin Plastic Quad Flatpack (PCM Suffix) 5 V
●• Eight Extended-Precision Registers
●• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
●• Two Low-Power Modes
●• Two- and Three-Operand Instructions
●• Parallel Arithmetic Logic Unit (ALU) and Multiplier Execution in a Single Cycle
●• Block-Repeat Capability
●• Zero-Overhead Loops With Single-Cycle Branches
●• Conditional Calls and Returns
●• Interlocked Instructions for Multiprocessing Support
●• One External Pin, PRGW, That Configures the External-Program-Memory Width to 16 or 32 Bits
●• Two Sets of Memory Strobes (STRB0 and STRB1) and One I/O Strobe (IOSTRB) Allow Zero-Glue Logic Interface to Two Banks of Memory and One Bank of External Peripherals
●• Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation, External Memory Width, and Data Type Size
●• STRB0 and STRB1 Memory Strobes Handle 8-, 16-, or 32-Bit External Data Accesses (Reads and Writes)
●• Multiprocessor Support Through the HOLD and HOLDA Signals Is Valid for All Strobes
