description
●The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point processors manufactured in 0.6-µm triple-level-metal CMOS technology. The devices are part of the SMJ320C3x generation of DSPs from Texas Instruments.
●Processed to MIL-PRF-38535 (QML)
●Operating Temperature Ranges:
● − Military (M) −55°C to 125°C
● − Special (S) −55°C to 105°C
●SMD Approval
●High-Performance Floating-Point Digital Signal Processor (DSP):
● − SMJ320C31-60 (5 V)
● 33-ns Instruction Cycle Time
● 330 Million Operations Per Second
● (MOPS), 60 Million Floating-Point
● Operations Per Second (MFLOPS),
● 30 Million Instructions Per Second(MIPS)
●− SMJ320C31-50 (5 V)
● 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS
●− SMJ320C31-40 (5 V)
● 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
●− SMJ320LC31-40 (3.3 V)
● 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
●− SMQ320LC31-40 (3.3 V)
● 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS
●32-Bit High-Performance CPU
●16- /32-Bit Integer and 32- /40-Bit Floating-Point Operations
●32-Bit Instruction and Data Words, 24-Bit Addresses
●Two 1K Word ×32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
●Boot-Program Loader
●64-Word ×32-Bit Instruction Cache
●Eight Extended-Precision Registers
●Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
●Two Low-Power Modes
●On-Chip Memory-Mapped Peripherals:
●− One Serial Port Supporting 8- /16- /24- /32-Bit Transfers
●− Two 32-Bit Timers
●− One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
●Fabricated Using Enhanced Performance Implanted CMOS (EPIC)Technology by Texas Instruments (TI)
●Two- and Three-Operand Instructions
●40 / 32-Bit Floating-Point /Integer Multiplier and Arithmetic Logic Unit (ALU)
●Parallel ALU and Multiplier Execution in a Single Cycle
●Block-Repeat Capability
●Zero-Overhead Loops With Single-Cycle Branches
●Conditional Calls and Returns
●Interlocked Instructions for Multiprocessing Support
●Bus-Control Registers Configure Strobe-Control Wait-State Generation
●Validated Ada Compiler
●Integer, Floating-Point, and Logical Operations
●32-Bit Barrel Shifter
●One 32-Bit Data Bus (24-Bit Address)
●Packaging
●− 132-Lead Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix)
●− 141-Pin Ceramic Staggered Pin Grid- Array Package (GFA Suffix)
●− 132-Lead TAB Frame
●− 132-Lead Plastic Quad Flatpack (PQ Suffix)
